This invention relates generally to memory fabrication, and more specifically to a method for achieving high self-aligning vertical gate studs relative to the support isolation level.
A driving motivator in commercial memory cells design and architecture is the desire to pack more memory capability into a smaller integrated circuit. This goal necessarily involves competing trade-offs in cost, circuit complexity, power dissipation, yield, performance, and the like. Trench capacitors are known in the art as an architecture whereby the overall size (in terms of surface area or chip xe2x80x9creal estatexe2x80x9d) of the memory cell is reduced. The size reduction is accomplished by taking a planar capacitor element of the memory cell and forming the capacitor instead in a trench, also known as a deep trench. As is known in the art, a typical DRAM cell includes a capacitor upon which is stored a charge (or no charge depending upon the cell""s state) and a pass transistor, which is used to charge the capacitor during writing and in the read process to pass the charge on the capacitor to a sense amplifier. Yet further improvement in device geometry and performance is accomplished by forming the pass transistor vertically as well, preferably in the upper region of the deep trench in which the trench capacitor is formed.
In current DRAM microchip fabrication, another trench, an isolation trench, isolates the different cells of the memory chip from one another. The isolation trench attenuates various problems associated with densely packed memory cells, such as out diffusion of buried layers, leakage current, and the like.
In one stage of the manufacturing process of the memory chip, such as the DRAM chip, the isolation trench is typically filled with isolation trench oxide (ITO) to help the isolation trench perform its isolation function. However, at some point in the chip fabrication, the isolation trench with its ITO must be planarized, so that the proper electrical connections can be made over the isolation trench without an electrical short being produced.
In the prior art, the height of the planarization of the isolation trench is determined by the height of a pad nitride layer, a temporary isolation layer covering the silicon region surrounding the deep trench. Whatever the height of the pad nitride layer, this will also be the height at which the isolation trench is planarized. There is a maximum allowable height for the isolation trench after planarization; otherwise the step height between the isolation trench and the adjacent silicon region would be too high. This excessive step height causes subsequent difficulties in the manufacturing process. For instance, in a subsequent processing step, word lines are formed to interconnect the various memory cells in the array and these word lines must cross over the step. The word line material, typically tungsten or tungsten silicide, may not be completely etched away in the region of the step height when patterning the word lines, resulting in short circuits between adjacent word lines. Therefore, the top of the pad nitride should be set to a low level to enable a sufficient degree of planarization of the isolation trench without causing excessive step height.
However, there is also a minimum height for vertical gate studs that are required to contact the word lines. These vertical gate studs need to be high enough to protrude above an array top oxide (ATO) that is formed over the array region. The ATO ensures that passing word lines are sufficiently isolated from the active regions. The vertical gate studs, however, need to contact the active word lines. Therefore, the vertical gate stud should be designed to be sufficiently high to allow a sufficient amount of array top oxide to insulate a passing word line from any unwanted interactions with any active regions.
However, in the prior art, the planarization of the isolation trench to the height of the pad nitride layer also disadvantageously determines the height of vertical gate studs. The isolation trench and the vertical gate studs are both chemically-mechanically polished (CMP) simultaneously to the level of the pad nitride surrounding the vertical gate stud, with the layer of array top oxide added afterwards. The polishing step has no way of discerning the isolation trench and the vertical gate stud.
This above correspondence between the height of the pad nitride and both the IT and the vertical gate studs creates a dilemma. The above constraints, a lower pad nitride height for the planarization of the isolation trench, but a higher pad nitride height to create higher vertical gate studs, create conflicting demands. It would be advantageous to have a method of manufacture of a higher vertical gate stud height that is not dictated by either the height of the pad nitride or the need to planarize the support isolation trench. Therefore what is needed in the art is a method of creating higher vertical gate studs that overcome the deficiencies of the prior art.
In one aspect, the present invention provides for a method of fabricating a vertical gate transistor. The method includes forming a trench in a semiconductor substrate, the area of the trench being defined in at least one direction by a pad layer formed atop the semiconductor substrate and forming a gate conductor in the trench. The method further includes forming a recess within the trench and partially filling the recess with a conformal conductive layer while leaving a first recess within the conformal conductive layer and at least partially filling the first recess with a second conductive layer. The conformal layer is etched to a level substantially coplanar with the pad layer, after which the pad layer is removed. The method further includes etching back the conformal conductive layer to a level below a top surface of the semiconductor substrate, forming a liner layer atop the semiconductor substrate, the gate conductor, and the second conductive layer.
In another aspect, the invention provides for a vertical gate transistor comprising a trench formed within a semiconductor substrate, a gate oxide formed on the sidewall of the trench, and a gate conductor formed within the trench. The transistor further includes a vertical gate stud protruding above the surface of the semiconductor substrate. The vertical gate stud includes a conductive first region contacting the gate conductor formed within the trench and extending a first distance above the semiconductor substrate, a conductive second region contacting the first region and extending above the first region, the conductive second region and first conductive region having differing etch resistance characteristics, and a gate contact formed above and contacting said second conductive region.
In yet another aspect, the present invention provides for a memory cell comprising a trench formed within a top surface of a semiconductor substrate, a capacitor formed within a lower portion of the trench, comprising a buried layer adjacent the trench, an insulator layer formed on a sidewall of the trench, and a conductor formed within the lower portion of the trench, and a conductive buried strap region electrically coupled to the capacitor. The memory cell further includes a gate oxide formed on a sidewall of an upper portion of the trench and a gate conductor formed within the upper portion of the trench. The memory cell further includes a gate stud extending above the top surface of the semiconductor substrate. The gate stud includes a first material formed on the gate conductor, the first material being subject to etching by a pre-selected etchant and second material formed on the first material and being resistant to etching by the pre-selected etchant. The first material and the second material provide a conductive element that extends the gate conductor to a level of a wiring layer above the memory cell.